CALIFORNIA STATE POLYTECHNIC UNIVERSITY, POMONA
Electrical and Computer Department

Integrated Circuits: Devices and Modeling

ECE 412
Fall 2007
Class Nbr: 73332
Meets: MW 12:00 to 1:50 PM
Instructor: Dr. R. L. Bernick
Office: Bldg. 9, Rm. 415
Phone: (909) 869-2518
Email: rlbernick@csupomona.edu
Office Hours: MW 10:45 AM – 12:00 noon
Final Exam: Wednesday, December 5, 11:30 AM – 1:30 PM
Text: H. Craig Casey, Devices for Integrated Circuits, Wiley, 1999.

References: Kano, Semiconductor Devices, Prentice Hall, 1998.
Pierret, Semiconductor Device Fundamentals, Addison Wesley, 1996.
Streetman and Banerjee, Solid State Electroinic Devices, 5th Edition,
                             Prentice Hall, 2000 (or earlier editions of Streetman).

Course Outline

Topic Text Reference
Review of Semiconductor Electronics                                           Chapters 1 to 3
Review of pn Junctions                                                                  Chapters 4 and 5
Metal - Semiconductor Systems                                                      Chapter 6
MOS Capacitors and CCDs                                                           Chapter 7
MOSFETs                                                                                      Chapter 8


               Grading:
                    Computer Assignments 15%
                    Term Paper 25%
                    Midterm Exam 25%
                    Final Exam 35%

Homework, assigned and collected approximately weekly, is checked but not graded. It can affect grade in borderline cases. Late homework not accepted.

Homework Answers

Drop policy: See the University Catalog for the College of Engineering drop policy.