| Final Exam |
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| CS 210 Fall 1999 Craig A. Rich |
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Consider the Boolean expression e = (x(y'+z)'+y)'z.
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Design a combinatorial circuit that implements the sum of minterms expression e = Sigma(1,2,3,...,14) using a 2-level XOR-OR circuit (XOR gates at level 1 and an OR gate at level 2). |
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In the following implementation of a full adder, show that the carry output (C) implements a three-input majority circuit. ![]() |
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A 4-bit increment-decrement circuit has 5 inputs (A4, A3, A2, A1, M) and 5 outputs (C5, S4, S3, S2, S1), where A4A3A2A1, C5, and S4S3S2S1 play the same role as in a 4-bit adder, and M selects that the sum S is obtained from the operand A by adding one (increment, M = 0) or subtracting one (decrement, M = 1). Implement a 4-bit increment-decrement circuit using a 4-bit full adder and inverters. |
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Consider the Boolean expression e = ((x'+z)'+y')'.
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Analyze the following sequential circuit. Give a minimized Boolean expression for each circuit output and flip-flop input, a state table, and a state diagram showing all states. ![]() |
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Design a sequential circuit which implements the following state diagram using T flip-flops. ![]() |