| Basic
Unix Commands:
List
of common commands (Stanford University)
The
first time you use Cadence:
Opening an Xwindow launching Cadence at Cal Poly Pomona
Cadence
environment introduction
Starting
Cadence:
Opening an Xwindow launching Cadence at Cal Poly Pomona
Bindkey
Summary
Schematic
Entry - Virtuoso-Schematic
all - Initializing
the Schematic Composer Environment - First
time only
ECE 423, 418, 423L - Creating
a schematic of a nor2
ECE423 - schematic
for determining fanout of 4 delay
ECE423L -Creating
a Heirarchical schematic
ECE423L -Creating
Heirarchical schematic for a transient simulation
More
efficient way to name pins and wires
ECE 423, 418, 423L - Creating
Symbols
ECE 418, 407 -Creating a schematic to characterize
a PMOS transistor
Working with buses and arrays
Simulating
- Analog-Artist
all - Initializing
your simulation environment - First
time only
all - Parts
to use for simulations (Voltage and Current sources)
all - Loading
a State
ECE 407, ECE 418 - Running
a DC sweep simulation
ECE 407 - Running
a Parametric Sweep Simulation
ECE 423L - Running
a Transient Simulation
ECE 423 - Characterizing
an inverter with a fanout of 4
Nested Sweep
Plotting
Simulation Results - Waveform Window
Plotting
Transient Simulations
Plotting
DC Simulations
ECE 407, 418 - Plotting ro
Layout
ECE 423L - NOR
Layout Example
(with labels)
ECE 423, 418 - NOR
Layout Example (no labels)
DRC
LVS --- Debugging
LVS errors
ECE 423L -Hierarchical
Layout
Mosis design rules
We are using the sub-micron design rules: SCMOS_SUBM
The particular flavor that we are using is:
SCNME_SUBM
How
to access the Cadence manual (cdsdoc) - tutorials and documentation
Install Directory: /usr/local/cadence/ic50
Virtuoso
Users Guide
We wish to acknowledge North Carolina State University for developing
a the NCSU design kit and making it available
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