Room 9-503

Application Specific Integrated Circuit

(ASIC) Design Lab

Lab Director: Rajan Chandra

Courses Offered:

ECE204L, ECE 308L, ECE 408L, ECE 414L, ECE415L, ECE 425L ,ECE 424L, Group Senior Project

Laboratory Size: 1321 square feet

Average # of students per year: 323

Lab Function:

The purpose of this lab is to provide necessary support to the lab classes that are associated with popular digital option senior level design courses such as ECE 424L (State Machine Design) and ECE 425L (Computer Architecture). Specifically, students should be able to design systems such as CRC generator, Single Cycle RISC CPU and be able to target these designs to a complex PLD or FPGA.

Lab Status:

Currently, there is a great demand for individuals who can design medium scale prototype digital systems whose gate complexity is approximately 3000 gates. Since the market is very much competitive, a prototype must be developed within 2 or 3 months. In order to deal with this situation, practicing digital design engineers always lean on front end CAD tools and back end tools such as FPGA development systems. Therefore, unless we train our students in these areas, they cannot succeed in their job hunt.

This room houses twelve laboratory benches each equipped with:

• DMM (Beckman, Tech 300)
• Digital Oscilloscope 
• 12 TI TMS320C6711 DSK DSP Board
• Function Generator (Tektronix, CFG250)
• Power Supply (Systron, TL8-3)
• Pulse Generator (Datap JLse , 109)
• 12 Computers (HP)

The room houses also PLD programmer.

Current Problems with the Laboratory:

1. Equipment and computers need to be upgraded.

Equipment Needs:

1. Twelve new computers.
2. Twelve DMMs
3. Twelve Power Supplies
4. Twelve Function Generators